- K.-H. Chang, I. L. Markov, V. Bertacco, "Functional Design Errors in Digital Circuits: Diagnosis, Correction and Repair", Springer 2009. (ISBN: 978-1-4020-9364-7), Order from Amazon

- K.-H. Chang, H.-Z. Chou, H. Yu, D. Dobbyn and S.-Y. Kuo, "Handling Nondeterminism in Logic Simulation So That Your Waveform Can Be Trusted Again", IEEE Design and Test of Computers, to appear
- K.-H. Chang and C. Browy, "Parallel Logic Simulation -- A Myth or Reality?", IEEE Computer, vol. 45, no. 4, Apr. 2012, pp. 67-73
- K.-H. Chang, V. Bertacco, I. L. Markov and A. Mishchenko, "Logic Synthesis and Circuit Customization Using Extensive External Don't-Cares," ACM Transactions on Design Automation of Electronic Systems, Vol. 15, No. 3, Article 26, 2010
- H.-Z. Chou, K.-H. Chang and S.-Y. Kuo, "Accurately Handle Don't-Care Conditions in High-Level Designs and Application for Reducing Initialized Registers", IEEE Trans. on Computer-Aided Design, Apr. 2010, pp. 646-651.
- K.-H. Chang, D. A. Papa, I. L. Markov, V. Bertacco, "InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization", IEEE Design and Test of Computers, vol. 26, no. 2, Mar 2009, pp. 34-43
- K.-H. Chang, I. L. Markov and V. Bertacco, "Automating Post-Silicon Debugging and Repair", IEEE Computer, vol. 41, no. 7, Jul. 2008, pp. 47-54.
- K.-H. Chang, I. L. Markov, V. Bertacco, "SafeResynth: A New Technique for Physical Synthesis", Integration: the VLSI Journal, Jul. 2008, pp. 544-556.
- K.-H. Chang, I. L. Markov, V. Bertacco, "Fixing Design Errors with Counterexamples and Resynthesis," IEEE Trans. on Computer-Aided Design, Jan. 2008, pp. 184-188.
- K.-H. Chang, I. L. Markov and V. Bertacco, "Post-placement Rewiring by Exhaustive Search for Functional Symmetries," ACM Transactions on Design Automation of Electronic Systems, Vol. 12, No. 3, Article 32, Aug. 2007.
- K.-H. Chang, V. Bertacco and I. L. Markov, "Simulation-based Bug Trace Minimization with BMC-based Refinement," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, NO. 1, Jan. 2007, pp. 152-165.

- T.-W. Chiang, K.-H. Chang, Y.-T. Liu and J.-H. R. Jiang, "Scalable Sequence-Constrained Retention Register Minimization in Power Gating Design", Design Automation Conference (DAC), San Francisco, CA, Jun. 2015, Session 57.4
- K.-H. Chang, Y.-T. Liu and C. Browy, "Automated Methods for Eliminating X Bugs", Proc. Int'l Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, Mar 2014, pp. 597-603.
- K.-H. Chang, C.-W. Chang, J.-H. R. Jiang and C.-N. J. Liu, "Reducing Test Point Overhead Using Don't-Cares", IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Boise, ID, Aug. 2012, pp. 534-537.
- K.-H. Chang, C.-W. Chang, J.-H. R. Jiang and C.-N. J. Liu, "Improving Design Verifiability by Early RTL Coverability Analysis", ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE), Arlington, VA, Jul. 2012, pp. 25-32.
- K.-H. Chang and C. Browy, "Improving Gate-level Simulation Accuracy when Unknowns Exist", Design Automation Conference (DAC), San Francisco, CA, Jun. 2012, pp. 936-940.
- K.-H. Chang, H.-Z. Chou and I. L. Markov, "RTL Analysis and Modifications for Improving At-speed Test", Proc. Design Autom. and Test in Europe (DATE), Dresden, Germany, March 2012, pp. 400-405.
**(Best Paper Award nominee)** - C.-N. Chung, C.-W. Chang, K.-H. Chang and S.-Y. Kuo, "Applying Verification Intention for Design Customization via Property Mining under Constrained Testbenches", ACM/IEEE Intl. Conf. Computer Design (ICCD), Amherst, MA, 2011, pp. 84-89.
- C.-W. Chang, H.-Z. Chou, K.-H. Chang, J.-H. R. Jiang, C.-N. J. Liu, C.-H. Hsiao and S.-Y. Kuo, "Constraint Generation for Software-Based Post-Silicon Bug Masking with Scalable Resynthesis Technique for Constraint Optimization", Proc. Int'l Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, Mar 2011, pp. 174-181.
- C.-N. Chung, C.-W. Chang, K.-H. Chang and S.-Y. Kuo, "Formal Reset Recovery Slack Calculation at the Register Transfer Level", Proc. Design Autom. and Test in Europe (DATE), Grenoble, France, Mar. 2011, pp. 571-574.
- H.-Z. Chou, K.-H. Chang and S.-Y. Kuo, "Facilitating Unreachable Code Diagnosis and Debugging", Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), Yokohama, Japan, January 2011, pp. 485-490.
- H.-Z. Chou, H. Yu, K.-H. Chang, D. Dobbyn and S.-Y. Kuo, "Finding Reset Nondeterminism in RTL Designs -- Scalable X-Analysis Methodology and Case Study", Proc. Design Autom. and Test in Europe (DATE), Dresden, Germany, Mar. 2010, pp. 1494-1499
- H.-Z. Chou, K.-H. Chang and S.-Y. Kuo, "Optimizing Blocks in an SoC Using Symbolic Code-Statement Reachability Analysis", Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), Taipei, Taiwan, January 2010, pp. 787-792.
- H.-Z. Chou, K.-H. Chang and S.-Y. Kuo, "Handling Don't-Care Conditions in High-Level Synthesis and Application for Reducing Initialized Registers", Design Automation Conference (DAC), San Francisco, CA, July 2009, pp. 412-415.
- H.-Z. Chou, I.-H. Lin, C.-S. Yang, K.-H. Chang and S.-Y. Kuo, "Enhancing Bug Hunting Using High-Level Symbolic Simulation", Great Lakes Symp. on VLSI (GLSVLSI), Boston, MA, May 2009, pp. 417-420.
- K.-H. Chang, V. Bertacco, I. L. Markov, "Customizing IP Cores for System-on-Chip Designs Using Extensive External Don't-Cares", Proc. Design Autom. and Test in Europe (DATE), Nice, France, April 2009, pp. 582-585.
- K.-H. Chang, I. L. Markov, and V. Bertacco, "Reap What You Sow: Spare Cells for Post-Silicon Metal Fix", Int'l Symposium on Physical Design (ISPD), Portland, OR, 2008, pp. 103-110.
- K.-H. Chang, I. Wagner, V. Bertacco, and I. L. Markov, "Automatic Error Diagnosis and Correction for RTL Designs", IEEE Int'l High Level Design Validation and Test Workshop (HLDVT), Irvine, CA, Nov. 2007, pp. 65-72.
- K.-H. Chang, I.L. Markov and V. Bertacco, "Automating Post-Silicon Debugging and Repair," Proc. Int'l Conf. on Computer-Aided Design (ICCAD), San Jose, CA, November 2007, pp. 91-98
- K.-H. Chang, D. A. Papa, I. L. Markov and V. Bertacco, "InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization", Proc. Int'l Symposium on Quality Electronic Design (ISQED) San Jose, CA, March 2007, pp. 487-492
- K.-H. Chang, I. L. Markov and V. Bertacco, "Safe Delay Optimization for Physical Synthesis", Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), Yokohama, Japan, January 2007, pp. 628-633
- S. Plaza, K.-H. Chang, I. L. Markov and V. Bertacco, "Node Mergers in the Presence of Don't Cares", in Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), Yokohama, Japan, January 2007, pp. 414-419
- K.-H. Chang, I. L. Markov and V. Bertacco, "Fixing Design Errors with Counterexamples and Resynthesis", in Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), Yokohama, Japan, January 2007, pp. 944-949
- K.-H. Chang, I. L. Markov and V. Bertacco, "Post-Placement Rewiring and Rebuffering by Exhaustive Search For Functional Symmetries," Proc. Int'l Conf. Computer-Aided Design (ICCAD), 2005, pp. 56-63
- K.-H. Chang, V. Bertacco and I. L. Markov, "Simulation-based Bug Trace Minimization with BMC-based Refinement," Proc. Int'l Conf. Computer-Aided Design (ICCAD), 2005, pp. 1045-1051
- K.-H. Chang, J.-Y. Kang, H.-W. Wang, W.-T. Tu, Y.-J. Yeh and S.-Y. Kuo, "Automatic Partitioner for Behavior Level Distributed Logic Simulation," Proc. Int'l Conf. Formal Techniques for Networked and Distributed Systems (FORTE), Oct. 2005, Taipei, Taiwan, LNCS 3731, pp 525-528

- K.-H. Chang, W.-T. Tu, H.-W. Wang, Y.-J. Yeh, and S.-Y. Kuo, "Techniques to Reduce Synchronization in Distributed Parallel Logic Simulation," Proceedings of the 16th IASTED International Conference on Parallel and Distributed Computing and Systems(PDCS'04), November 2004, Cambridge, MA, USA

- K.-H. Chang, W.-T. Tu, Y.-J. Yeh, and S.-Y. Kuo, "A Temporal Assertion Extension to Verilog," Proceedings of the 2nd International Symposium on Automated Technology for Verification and Analysis(ATVA04), October 2004, Taipei, Taiwan, LNCS 3299, pp 499-504

- C.-C. Yu, K.-H. Chang, Y.-J. Yeh, and S.-Y. Kuo, "System Level Assertion-Based Verification Environment for PCI/PCI-X and PCI-Express," VLSI Design/CAD Symposium, Taiwan, 2004

- K.-H. Chang, H.-W. Wang, Y.-J. Yeh, and S.-Y. Kuo, "Automatic Partitioner for Distributed Parallel Logic Simulation," IASTED International Conference on Modelling, Simulation and Optimization(MSO'04), Kauai, Hawaii, USA, 2004

- K.-H. Chang, W.-T. Tu, Y.-J. Yeh, and S.-Y. Kuo, "A Tag-Augmented Temporal Logic Checker," VLSI Design/CAD Symposium, Taiwan, 2003

- K.-H. Chang, Y.-C. Su, W.-T. Tu, Y.-J. Yeh, and S.-Y. Kuo, "A PCI-X Verification Environment Using C and Verilog," VLSI Design/CAD Symposium, Taiwan, 2003

- Y.-J. Yeh, K.-H. Chang, M.-T. Chen, and S.-Y. Kuo, "Compiled-code Technique for RTL Designs," VLSI Design/CAD Symposium, Taiwan, 2001

- K.-H. Chang, Y.-T. Liu and C. Browy, "Automated Method Eliminates X Bugs in RTL and Gates", Design Automation Conference (DAC), Austin, TX, Jun. 2013, Designer Track Poster
- K.-H. Chang, C.-W. Chang, J.-H. R. Jiang and C.-N. J. Liu, "Generating Local Test Point Activation Signals Using Controllability Don't-Cares", Int'l Workshop on Logic and Synthesis (IWLS), Berkeley, CA, 2012, pp. 180-184
- C.-N. Chung, C.-W. Chang, K.-H. Chang and S.-Y. Kuo, "Applying Verification Intention for Design Customization via Property Mining under Constrained Testbenches", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), San Diego, CA, 2011, pp. 123-128
- K.-H. Chang, C.-W. Chang, J.-H. R. Jiang and C.-N. J. Liu, "Improving Design Verifiability by Early RTL Coverability Analysis", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), San Diego, CA, 2011, pp. 183-188
- K.-H. Chang, H.-Z. Chou and I. L. Markov, "Improving Path Delay Testability at Early Design Stages", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), San Diego, CA, 2011, pp. 24-31
- H.-Z. Chou, K.-H. Chang and S.-Y. Kuo, "Automating Unreachable Code Diagnosis and Debugging", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), Irvine, CA, 2010, pp. 117-123
- H.-Z. Chou, C.-W. Chang, K.-H. Chang and S.-Y. Kuo, "Automatic Constraint Generation for Software-Based Post-Silicon Bug Repair", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), Irvine, CA, 2010, pp. 63-68
- H.-Z. Chou, K.-H. Chang and S.-Y. Kuo, "Achieving High Quality Verification at Early Design Phases via Native Symbolic Methodologies", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), Berkeley, CA, 2009, pp. 50-55.
- K.-H. Chang, V. Bertacco, I. L. Markov, and A. Mishchenko, "Synthesis with External Don't-Cares Using Shannon Entropy and Craig Interpolation", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), Lake Tahoe, CA, 2008
- K.-H. Chang, I. Wagner, V. Bertacco, and I. L. Markov, "Automatic Error Diagnosis and Correction for RTL Designs", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), San Diego, CA, May 2007, pp. 106-113.
- K.-H. Chang, I. L. Markov, and V. Bertacco, "Automating Post-Silicon Debugging and Repair", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), San Diego, CA, May 2007, pp. 114-121.
- K.-H. Chang, I. L. Markov, and V. Bertacco, "Fast Verification of Retiming", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), San Diego, CA, May 2007, pp. 165-166.
- K.-H. Chang, D. A. Papa, I. L. Markov and V. Bertacco, "Fast Simulation and Equivalence Checking Using OAGear", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), Denver, CO, June 2006, pp. 270-271.
- K.-H. Chang, I. L. Markov and V. Bertacco, "Keeping Physical Synthesis Safe and Sound", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), Denver, CO, June 2006, pp. 86-93.
- K.-H. Chang, J.-Y. Kang, C.-L. Huang, J. P. Hayes and I. L. Markov, "Fast Test Simulation via Distributed Computing," Technical paper, Avery Design Systems, 2006
- K.-H. Chang, I. L. Markov and V. Bertacco, "Post-Placement Rewiring and Rebuffering by Exhaustive Search for Functional Symmetries," ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), Lake Arrowhead, CA, June 2005, pp. 469-476.

- K.-H. Chang, W.-T. Tu, Y.-J. Yeh, and S.-Y. Kuo, "A Simulation-Based Temporal Assertion Checker for PSL," IEEE International Midwest Symposium on Circuits and Systems(MWSCAS'03), Cairo, Egypt, 2003

- K.-H. Chang, Y.-T. Liu, C. Browy and C. Huang, "Systems and Methods for Tracing and Fixing Unknowns in Gate-level Simulation", United States Patent 9058452, Jun 16, 2015
- K.-H. Chang, Y.-T. Liu, C. Browy and C. Huang, "Systems and Methods for Partial Retention Synthesis", United States Patent 8938705, Jan 20, 2015
- K.-H. Chang, Y.-T. Liu, C. Browy and C. Huang, "System and Method for Correcting Gate-level Simulation When Unknowns Exist", United States Patent 8402405, Mar 19, 2013
- K.-H. Chang, I. Wagner, V. Bertacco, and I. L. Markov,"Automatic Error Diagnosis and Correction for RTL Designs", United States Patent 8365110, Jan. 29, 2013
- K.-H. Chang, C. Browy, Y.-T. Liu and C. Huang, "Methods for Biasing Logic Simulation toward Exposing Design Errors Masked by X-Optimism", United States Provisional Patent Application 61663164, Jun. 22, 2012

- K.-H. Chang, J.-T. Fan, and S.-Y. Kuo, "Design and Implementation of Mandarin-to-Hakka Translation and Speech Synthesis System," Center for Hakka Studies Newsletter, issue 7, Hakka Research Center, National Central University, 2005, pp 152-168.

- K.-H. Chang, J.-T. Fan, and S.-Y. Kuo, "A Talking Browser," Journal of Internet Technology, July 2001, pp 171-176
- K.-H. Chang, "Relationship between Hakka, Mandarin and Japanese Kanji and Its Application," Journal of Taiwan Language and Language Education Vol. 2, National Hsin-chu Teachers College, 2000, pp 79-90

- K.-H. Chang, "Implementation and Analysis of Remote Home Appliances and Security System," Communications of IICM, June 1999
- K.-H. Chang, "The Way to Use Other Languages to Aid the Study of Hakka Dialect," Hakka Magazine, June 1999
- K.-H. Chang, "Hakka Diactionary and Hakka Input Method," Hakka Magazine, October 1997

Email address:changkh@umich.edu